KM3NeT CLB  2.0
KM3NeT CLB v2 Embedded Software
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dev_mboot.h
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1 /*
2  * KM3NeT CLB v2 Firmware
3  *
4  * Copyright 2013 KM3NeT Collaboration
5  *
6  * All Rights Reserved.
7  *
8  *
9  * File : dev_mboot.h
10  * Created : July 2013
11  * Author : David Calvo
12  * Vincent van Beveren
13  */
14 
15 #ifndef DEV_MBOOT_H_
16 #define DEV_MBOOT_H_
17 
18 /**
19  * @file
20  *
21  * @ingroup devices
22  *
23  * This structure describes the multiboot device.
24  *
25  * Multiboot is now actually an interface to the ICAPE2 device.
26  */
27 
28 #include "dev_defs.h"
29 
30 // List of used ICAPE2 Commands
31 #define MBOOT_CMD_NULL 0x00
32 #define MBOOT_CMD_IPROG 0x0F //!< Trigger reconfiguration
33 #define MBOOT_CMD_LTIMER 0x11 //!< Reload watchdog
34 
35 #define MBOOT_WATCHDOG_FREQ 340000 //!< Worse case watchdog speed.
36 #define MBOOT_WATCHDOG_MAX 0x3FFFFFFF
37 
38 #define MBOOT_WBSTAR_32BIT_ADDR_SHIFT 8 //!< Bit-shift required for 32-bit addresses
39 
40 #define MBOOT_BOOTSTS_VALID_0 BIT(0) //!< Status 0 valid (current boot)
41 #define MBOOT_BOOTSTS_FALLBACK_0 BIT(1) //!< Fallback used
42 #define MBOOT_BOOTSTS_IPROG_0 BIT(2) //!< IProg issued
43 #define MBOOT_BOOTSTS_WTO_ERRO_0 BIT(3) //!< Watchdog Time Out error
44 #define MBOOT_BOOTSTS_ID_ERROR_0 BIT(4) //!< ID error
45 #define MBOOT_BOOTSTS_CRC_ERROR_0 BIT(5) //!< CRC error
46 #define MBOOT_BOOTSTS_WRAP_ERROR_0 BIT(6) //!< WRAP error
47 
48 #define MBOOT_BOOTSTS_VALID_1 BIT(0) //!< Status 1 valid (previous boot)
49 #define MBOOT_BOOTSTS_FALLBACK_1 BIT(1) //!< Fallback used
50 #define MBOOT_BOOTSTS_IPROG_1 BIT(2) //!< IProg issued
51 #define MBOOT_BOOTSTS_WTO_ERRO_1 BIT(3) //!< Watchdog Time Out error
52 #define MBOOT_BOOTSTS_ID_ERROR_1 BIT(4) //!< ID error
53 #define MBOOT_BOOTSTS_CRC_ERROR_1 BIT(5) //!< CRC error
54 #define MBOOT_BOOTSTS_WRAP_ERROR_1 BIT(6) //!< WRAP error
55 
56 #define MBOOT_TIMER_VALUE_MASK 0x3FFFFFFF //!< Mask for timer
57 #define MBOOT_TIMER_USR_MON BIT(31) //!< User watchdog
58 #define MBOOT_TIMER_CFG_MON BIT(30) //!< Configuration watchdog.
59 
60 #define MBOOT_BSPI_SPI_OPCODE_MASK 0x000000FF
61 #define MBOOT_BSPI_SPI_OPCODE_SHIFT 0
62 #define MBOOT_BSPI_SPI_BUSWIDTH_MASK 0x00000300
63 #define MBOOT_BSPI_SPI_BUSWIDTH_SHIFT 8
64 #define MBOOT_BSPI_SPI_24BIT_MASK 0x00000001 //!< If set, its a 24 bit read command
65 
66 
67 /**
68  * Structure defines ICAPE2 registers (historically named 'Multiboot')
69  */
70 typedef struct
71 {
72  reg_io CRC; //!< CRC Register
73  reg_io FAR; //!< Frame Address Register
74  reg_o FDRI; //!< Frame data register in
75  reg_i FDRO; //!< Frame data register out
76  reg_io CMD; //!< Command register
77  reg_io CTL0; //!< Control register
78  reg_io MASK; //!< Mask register
79  reg_i STAT; //!< Status register
80  reg_o LOUT; //!< Legacy output register
81  reg_io COR0; //!< Configuration Option 0 register
82  reg_o MFWR; //!< Multi Frame Write Register
83  reg_o CBC; //!< Initial CBC value register
84  reg_io IDCODE; //!< Device ID register
85  reg_io AXSS; //!< User Access Register
86  reg_io COR1; //!< Configuration Option 1 register
87  reg_i __res0F;
88  reg_io WBSTAR; //!< Warm Boot Start Address
89  reg_io WTIMER; //!< Watchdog Timer Register
90  reg_i __res12;
91  reg_i __res13;
92  reg_i __res14;
93  reg_i __res15;
94  reg_i BOOTSTS; //!< Boot History Status Register
95  reg_i __res17;
96  reg_io CTL1; //!< Control register 1
97  reg_i __res19;
98  reg_i __res1A;
99  reg_i __res1B;
100  reg_i __res1C;
101  reg_i __res1D;
102  reg_i __res1E;
103 
104  reg_io BSPI; //!< BPI/SPI configuration options
105 } MBOOT_Device;
106 
107 
108 #endif /* DEV_MBOOT_H_ */
volatile unsigned int CRC
CRC Register.
Definition: dev_mboot.h:72
volatile unsigned int BSPI
BPI/SPI configuration options.
Definition: dev_mboot.h:104
volatile unsigned int MASK
Mask register.
Definition: dev_mboot.h:78
volatile unsigned int FAR
Frame Address Register.
Definition: dev_mboot.h:73
volatile unsigned int MFWR
Multi Frame Write Register.
Definition: dev_mboot.h:82
volatile unsigned int IDCODE
Device ID register.
Definition: dev_mboot.h:84
volatile unsigned int WTIMER
Watchdog Timer Register.
Definition: dev_mboot.h:89
volatile unsigned int COR0
Configuration Option 0 register.
Definition: dev_mboot.h:81
volatile unsigned int CTL1
Control register 1.
Definition: dev_mboot.h:96
const volatile unsigned int BOOTSTS
Boot History Status Register.
Definition: dev_mboot.h:94
#define reg_i
Read-only register.
Definition: dev_defs.h:39
const volatile unsigned int FDRO
Frame data register out.
Definition: dev_mboot.h:75
#define reg_o
Write-only register.
Definition: dev_defs.h:36
volatile unsigned int CBC
Initial CBC value register.
Definition: dev_mboot.h:83
volatile unsigned int AXSS
User Access Register.
Definition: dev_mboot.h:85
Structure defines ICAPE2 registers (historically named &#39;Multiboot&#39;)
Definition: dev_mboot.h:70
const volatile unsigned int STAT
Status register.
Definition: dev_mboot.h:79
volatile unsigned int FDRI
Frame data register in.
Definition: dev_mboot.h:74
#define reg_io
Input/Output register.
Definition: dev_defs.h:33
volatile unsigned int LOUT
Legacy output register.
Definition: dev_mboot.h:80
volatile unsigned int WBSTAR
Warm Boot Start Address.
Definition: dev_mboot.h:88
volatile unsigned int COR1
Configuration Option 1 register.
Definition: dev_mboot.h:86
volatile unsigned int CMD
Command register.
Definition: dev_mboot.h:76
volatile unsigned int CTL0
Control register.
Definition: dev_mboot.h:77
This module contains some very basic type definitions used for hardware mappings. ...