31 #define MBOOT_CMD_NULL 0x00
32 #define MBOOT_CMD_IPROG 0x0F
33 #define MBOOT_CMD_LTIMER 0x11
35 #define MBOOT_WATCHDOG_FREQ 340000
36 #define MBOOT_WATCHDOG_MAX 0x3FFFFFFF
38 #define MBOOT_WBSTAR_32BIT_ADDR_SHIFT 8
40 #define MBOOT_BOOTSTS_VALID_0 BIT(0)
41 #define MBOOT_BOOTSTS_FALLBACK_0 BIT(1)
42 #define MBOOT_BOOTSTS_IPROG_0 BIT(2)
43 #define MBOOT_BOOTSTS_WTO_ERRO_0 BIT(3)
44 #define MBOOT_BOOTSTS_ID_ERROR_0 BIT(4)
45 #define MBOOT_BOOTSTS_CRC_ERROR_0 BIT(5)
46 #define MBOOT_BOOTSTS_WRAP_ERROR_0 BIT(6)
48 #define MBOOT_BOOTSTS_VALID_1 BIT(0)
49 #define MBOOT_BOOTSTS_FALLBACK_1 BIT(1)
50 #define MBOOT_BOOTSTS_IPROG_1 BIT(2)
51 #define MBOOT_BOOTSTS_WTO_ERRO_1 BIT(3)
52 #define MBOOT_BOOTSTS_ID_ERROR_1 BIT(4)
53 #define MBOOT_BOOTSTS_CRC_ERROR_1 BIT(5)
54 #define MBOOT_BOOTSTS_WRAP_ERROR_1 BIT(6)
56 #define MBOOT_TIMER_VALUE_MASK 0x3FFFFFFF
57 #define MBOOT_TIMER_USR_MON BIT(31)
58 #define MBOOT_TIMER_CFG_MON BIT(30)
60 #define MBOOT_BSPI_SPI_OPCODE_MASK 0x000000FF
61 #define MBOOT_BSPI_SPI_OPCODE_SHIFT 0
62 #define MBOOT_BSPI_SPI_BUSWIDTH_MASK 0x00000300
63 #define MBOOT_BSPI_SPI_BUSWIDTH_SHIFT 8
64 #define MBOOT_BSPI_SPI_24BIT_MASK 0x00000001
volatile unsigned int CRC
CRC Register.
volatile unsigned int BSPI
BPI/SPI configuration options.
volatile unsigned int MASK
Mask register.
volatile unsigned int FAR
Frame Address Register.
volatile unsigned int MFWR
Multi Frame Write Register.
volatile unsigned int IDCODE
Device ID register.
volatile unsigned int WTIMER
Watchdog Timer Register.
volatile unsigned int COR0
Configuration Option 0 register.
volatile unsigned int CTL1
Control register 1.
const volatile unsigned int BOOTSTS
Boot History Status Register.
#define reg_i
Read-only register.
const volatile unsigned int FDRO
Frame data register out.
#define reg_o
Write-only register.
volatile unsigned int CBC
Initial CBC value register.
volatile unsigned int AXSS
User Access Register.
Structure defines ICAPE2 registers (historically named 'Multiboot')
const volatile unsigned int STAT
Status register.
volatile unsigned int FDRI
Frame data register in.
#define reg_io
Input/Output register.
volatile unsigned int LOUT
Legacy output register.
volatile unsigned int WBSTAR
Warm Boot Start Address.
volatile unsigned int COR1
Configuration Option 1 register.
volatile unsigned int CMD
Command register.
volatile unsigned int CTL0
Control register.
This module contains some very basic type definitions used for hardware mappings. ...