KM3NeT CLB  2.0
KM3NeT CLB v2 Embedded Software
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
cfg_soc.h
Go to the documentation of this file.
1 /*
2  * KM3NeT CLB v2 Firmware
3  *
4  * Copyright 2013 KM3NeT Collaboration
5  *
6  * All Rights Reserved.
7  *
8  *
9  * File : lm32_soc.h
10  * Created : 25 jan 2013
11  * Author : Vincent van Beveren
12  */
13 
14 #ifndef CFG_SOC_H_
15 #define CFG_SOC_H_
16 
17 /**
18  * @file
19  *
20  * @ingroup cfg
21  *
22  * Defines the configuration of the LM32 SOC for the CLBv2.
23  */
24 
25 #define CFG_SOC_CLBV2
26 
27 #define WISHBONE_FREQ 62500000
28 
29 
30 // -------------------------------------------------------------------------------------------- //
31 
32 /**
33  * SOC specific memory mapping.
34  */
35 #define SUART1_BASE (0x00020000UL) ///< WR Simple UART
36 #define TDC_BASE (0x00020100UL) ///< TDC device base
37 #define ACOU_BASE (0x00020200UL) ///< Acoustic device
38 #define GPIO_BASE (0x00020300UL) ///< GPIO device
39 #define SPI_BASE (0x00020400UL) ///< WR SPI device
40 #define I2C_BASE (0x00020500UL) ///< Real OpenCores I2C device
41 
42 /*
43  About 'Virtual' I2C Devices:
44  First there where physical I2C devices. However, to save space on the bus,
45  later these where combined in one I2C device, containing an interface mux.
46  To support this without having to modify all the code I've made virtual I2C
47  devices. These devices do not have a valid address space, but instead the I2C
48  driver converts address bits 7..4 of the address to an interface number.
49 
50  VvB - 11 Feb. 2014
51  */
52 #define I2C1_BASE (0x00020500UL) ///< Virtual OpenCores I2C1 device
53 #define I2C2_BASE (0x00020510UL) ///< Virtual OpenCores I2C2 device
54 #define I2C3_BASE (0x00020520UL) ///< Virtual OpenCores I2C3 device
55 
56 #define NANOB_BASE (0x00020600UL) ///< Nano-Beacon device base
57 
58 #define TIMER_BASE (0x00020700UL) ///< WR timer
59 
60 #define DATEREV_BASE (0x00020800UL) ///< Date/Revision device.
61 
62 #define XADC_BASE (0x00020900UL) ///< XADC device
63 
64 #define IPMCTRL_BASE (0x00020A00UL) ///< IPMUX control device base
65 #define STMACH_BASE (0x00020B00UL) ///< State Machine device base
66 #define MBOOT_BASE (0x00020C00UL) ///< Multiboot device base
67 
68 #define SUART2_BASE (0x00020D00UL) ///< WR Simple UART
69 #define SUART3_BASE (0x00020E00UL) ///< WR Simple UART
70 #define SUART4_BASE (0x00020F00UL) ///< WR Simple UART
71 
72 #define WATCHDOG_BASE (0x00021000UL) //!< Watchdog base address
73 #define IPMFIFO_BASE (0x00028000UL) ///< IPMUX FIFO device base
74 
75 
76 #define SDB_BASE (0x00040000UL) ///< Self Describing Bus
77 
78 // devices which are actually in the WRPC memory space.
79 #define PTP_OFFSET (0x00100000UL)
80 #define PTP_PPS_GEN (0x00020300UL | PTP_OFFSET) ///< PTP core PPS gen
81 #define PTP_VUART (0x00020500UL | PTP_OFFSET) ///< PTP core simple uart
82 
83 
84 #ifdef DUBASE
85 #define PTP_ROM_SIZE 69064
86 #else
87 #define PTP_ROM_SIZE 67968
88 #endif
89 
90 
91 /**
92  * WhiteRabbit exchange address, not a real device.
93  */
94 #define WRX_BASE (0x000001FF80) ///< WhiteRabbit eXchange.
95 
96 #define IRQ_DEBUG 0 //!< Debug button pressed
97 #define IRQ_TSLICE 1 //!< New timeslice.
98 #define IRQ_OVERFLOW 2 //!< Overflow
99 #define IRQ_NANOB 3 //!< Nano-beacon IRQ
100 #define IRQ_SUART1 4 //!< Simple Uart 1 Rx Byte
101 #define IRQ_SUART2 5 //!< Simple Uart 2 Rx Byte
102 #define IRQ_SUART3 6 //!< Simple Uart 3 Rx Byte
103 #define IRQ_SUART4 7 //!< Simple Uart 4 Rx Byte
104 #define IRQ_1HZ 8 //!< 1Hz IRQ for watchdog-like feature
105 #define IRQ_ROMXS 9 //!< Triggered when there is ROM access
106 
107 #define SYS_CRASH_COUNT 10 //!< After 10 seconds of no main-loop activity, reboot CLB.
108 #define SYS_RECONFIGURE_COUNT 2 //!< After 10 reboots, reconfigure
109 
110 #define UART_ID1 1
111 #define UART_ID2 2
112 #define UART_ID3 3
113 #define UART_ID4 4
114 
115 #ifdef DUBASE
116 #define UART_CFGS \
117  UART_CFG( UART_ID1, SUART1, IRQ_SUART1 ) \
118  UART_CFG( UART_ID2, SUART2, IRQ_SUART2 ) \
119  UART_CFG( UART_ID3, SUART3, IRQ_SUART3 ) \
120  UART_CFG( UART_ID4, SUART4, IRQ_SUART4 )
121 #else
122 #define UART_CFGS \
123  UART_CFG( UART_ID1, SUART1, IRQ_SUART1 )
124 #endif
125 
126 #define SPI_SPEED ( WISHBONE_FREQ / 2) ///< Maximum SPI speed = half WB speed
127 #define I2C_SPEED 90000 ///< Unfortunately 90K is set because AHRS messes up otherwise
128 
129 #define NET_RX_BUFFER 1514
130 
131 /**
132  * S25FL Flash memory map (64 MB, FPGA: 125T)
133  *
134  * Offset Size Description
135  * -------- -------- ----------------------------
136  * 00000000 00800000 Golden Image #1
137  * 00800000 00800000 Run-time Image 1
138  * 01000000 00800000 Run-time Image 2
139  * 01800000 00800000 Diagnostic Image
140  * 02000000 00800000 Block space (8MB)
141  * 02800000 00800000 Logging (8MB)
142  * 03000000 00800000 Crash images
143  * 03800000 00800000 Free / Reserved
144  */
145 
146 #define PAGE_SIZE 512
147 #define BLOCK_SIZE 512
148 #define BLOCK_BYTES ( PAGE_SIZE * BLOCK_SIZE )
149 
150 #ifdef CLBV2
151 #ifdef CLBV2X
152 #define FLASH_SPACING 0x01000000 ///! 16 MB spacing for the 325T
153 #else
154 #define FLASH_SPACING 0x00800000 ///! 8 MB spacing for the 160T
155 #endif
156 #define FLASH_MAX_IMAGES 4
157 #endif
158 #ifdef KC705
159 #define FLASH_SPACING 0x00C00000 ///!< 12 MB spacing for the 325T
160 #define FLASH_MAX_IMAGES 1
161 #endif
162 
163 /// The block space offset
164 #define BLOCKS_OFFSET ( FLASH_SPACING * FLASH_MAX_IMAGES )
165 #define BLOCKS_SIZE ( 0x800000 )
166 #define BLOCKS_SPACING BLOCK_BYTES
167 
168 #define BLS_RUNTIME 0 //!< Runtime information location
169 #define BLS_SFPINFO 1 //!< SFP information (wavelength and such)
170 
171 
172 // Persistent logging
173 #define LOGGING_OFFSET ( BLOCKS_OFFSET + BLOCKS_SIZE )
174 #define LOGGING_SIZE ( 0x800000 )
175 
176 #define CRASH_OFFSET ( LOGGING_OFFSET + LOGGING_SIZE )
177 #define CRASH_IMG_SIZE ( 128 * 1024 )
178 #define CRASH_SIZE ( 0x800000 )
179 
180 
181 
182 
183 
184 // SDB verbose output
185 //#define SDB_VERBOSE
186 
187 #endif /* CFG_SOC_H_ */
188