33 #define SDB_ID_SPI 0xDE04CA4D
35 #define SPI_CTL_CHAR_LEN_MASK 0x7F
36 #define SPI_CTL_CHAR_LEN_SHIFT 0
37 #define SPI_CTL_GO_BSY BIT( 8)
38 #define SPI_CTL_RX_NEG BIT( 9)
39 #define SPI_CTL_TX_NEG BIT(10)
41 #define SPI_CTL_MODE_MASK ( SPI_CTL_TX_NEG | SPI_CTL_RX_NEG)
42 #define SPI_CTL_MODE_0 ( SPI_CTL_TX_NEG )
43 #define SPI_CTL_MODE_1 ( SPI_CTL_RX_NEG )
44 #define SPI_CTL_MODE_2 ( SPI_CTL_RX_NEG )
45 #define SPI_CTL_MODE_3 ( SPI_CTL_TX_NEG )
47 #define SPI_CTL_LSB BIT(11)
48 #define SPI_CTL_IE BIT(12)
49 #define SPI_CTL_ASS BIT(13)
51 #define SPI_DIV_MASK 0xFFFF
Structure defines OpenCores SPI Device.
volatile unsigned int CTL
Control.
volatile unsigned int DIVIDER
Divider.
#define reg_io
Input/Output register.
volatile unsigned int SS
Slave Select.
This module contains some very basic type definitions used for hardware mappings. ...