KM3NeT CLB  2.0
KM3NeT CLB v2 Embedded Software
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cfg_soc.h File Reference

Defines the configuration of the LM32 SOC for the CLBv2. More...

Go to the source code of this file.

Macros

#define CFG_SOC_CLBV2
 
#define WISHBONE_FREQ   62500000
 
#define SUART1_BASE   (0x00020000UL)
 SOC specific memory mapping. More...
 
#define TDC_BASE   (0x00020100UL)
 TDC device base.
 
#define ACOU_BASE   (0x00020200UL)
 Acoustic device.
 
#define GPIO_BASE   (0x00020300UL)
 GPIO device.
 
#define SPI_BASE   (0x00020400UL)
 WR SPI device.
 
#define I2C_BASE   (0x00020500UL)
 Real OpenCores I2C device.
 
#define I2C1_BASE   (0x00020500UL)
 Virtual OpenCores I2C1 device.
 
#define I2C2_BASE   (0x00020510UL)
 Virtual OpenCores I2C2 device.
 
#define I2C3_BASE   (0x00020520UL)
 Virtual OpenCores I2C3 device.
 
#define NANOB_BASE   (0x00020600UL)
 Nano-Beacon device base.
 
#define TIMER_BASE   (0x00020700UL)
 WR timer.
 
#define DATEREV_BASE   (0x00020800UL)
 Date/Revision device.
 
#define XADC_BASE   (0x00020900UL)
 XADC device.
 
#define IPMCTRL_BASE   (0x00020A00UL)
 IPMUX control device base.
 
#define STMACH_BASE   (0x00020B00UL)
 State Machine device base.
 
#define MBOOT_BASE   (0x00020C00UL)
 Multiboot device base.
 
#define SUART2_BASE   (0x00020D00UL)
 WR Simple UART.
 
#define SUART3_BASE   (0x00020E00UL)
 WR Simple UART.
 
#define SUART4_BASE   (0x00020F00UL)
 WR Simple UART.
 
#define WATCHDOG_BASE   (0x00021000UL)
 Watchdog base address.
 
#define IPMFIFO_BASE   (0x00028000UL)
 IPMUX FIFO device base.
 
#define SDB_BASE   (0x00040000UL)
 Self Describing Bus.
 
#define PTP_OFFSET   (0x00100000UL)
 
#define PTP_PPS_GEN   (0x00020300UL | PTP_OFFSET)
 PTP core PPS gen.
 
#define PTP_VUART   (0x00020500UL | PTP_OFFSET)
 PTP core simple uart.
 
#define PTP_ROM_SIZE   67968
 
#define WRX_BASE   (0x000001FF80)
 WhiteRabbit exchange address, not a real device. More...
 
#define IRQ_DEBUG   0
 Debug button pressed.
 
#define IRQ_TSLICE   1
 New timeslice. More...
 
#define IRQ_OVERFLOW   2
 Overflow.
 
#define IRQ_NANOB   3
 Nano-beacon IRQ.
 
#define IRQ_SUART1   4
 Simple Uart 1 Rx Byte.
 
#define IRQ_SUART2   5
 Simple Uart 2 Rx Byte.
 
#define IRQ_SUART3   6
 Simple Uart 3 Rx Byte.
 
#define IRQ_SUART4   7
 Simple Uart 4 Rx Byte.
 
#define IRQ_1HZ   8
 1Hz IRQ for watchdog-like feature
 
#define IRQ_ROMXS   9
 Triggered when there is ROM access.
 
#define SYS_CRASH_COUNT   10
 After 10 seconds of no main-loop activity, reboot CLB. More...
 
#define SYS_RECONFIGURE_COUNT   2
 After 10 reboots, reconfigure.
 
#define UART_ID1   1
 
#define UART_ID2   2
 
#define UART_ID3   3
 
#define UART_ID4   4
 
#define UART_CFGS   UART_CFG( UART_ID1, SUART1, IRQ_SUART1 )
 
#define SPI_SPEED   ( WISHBONE_FREQ / 2)
 Maximum SPI speed = half WB speed.
 
#define I2C_SPEED   90000
 Unfortunately 90K is set because AHRS messes up otherwise.
 
#define NET_RX_BUFFER   1514
 
#define PAGE_SIZE   512
 S25FL Flash memory map (64 MB, FPGA: 125T) More...
 
#define BLOCK_SIZE   512
 
#define BLOCK_BYTES   ( PAGE_SIZE * BLOCK_SIZE )
 
#define BLOCKS_OFFSET   ( FLASH_SPACING * FLASH_MAX_IMAGES )
 The block space offset.
 
#define BLOCKS_SIZE   ( 0x800000 )
 
#define BLOCKS_SPACING   BLOCK_BYTES
 
#define BLS_RUNTIME   0
 Runtime information location.
 
#define BLS_SFPINFO   1
 SFP information (wavelength and such)
 
#define LOGGING_OFFSET   ( BLOCKS_OFFSET + BLOCKS_SIZE )
 
#define LOGGING_SIZE   ( 0x800000 )
 
#define CRASH_OFFSET   ( LOGGING_OFFSET + LOGGING_SIZE )
 
#define CRASH_IMG_SIZE   ( 128 * 1024 )
 
#define CRASH_SIZE   ( 0x800000 )
 

Detailed Description

Defines the configuration of the LM32 SOC for the CLBv2.

Definition in file cfg_soc.h.

Macro Definition Documentation

#define IRQ_TSLICE   1

New timeslice.

Definition at line 97 of file cfg_soc.h.

#define PAGE_SIZE   512

S25FL Flash memory map (64 MB, FPGA: 125T)

Offset Size Description


00000000 00800000 Golden Image #1 00800000 00800000 Run-time Image 1 01000000 00800000 Run-time Image 2 01800000 00800000 Diagnostic Image 02000000 00800000 Block space (8MB) 02800000 00800000 Logging (8MB) 03000000 00800000 Crash images 03800000 00800000 Free / Reserved

Definition at line 146 of file cfg_soc.h.

#define SUART1_BASE   (0x00020000UL)

SOC specific memory mapping.

WR Simple UART

Definition at line 35 of file cfg_soc.h.

#define SYS_CRASH_COUNT   10

After 10 seconds of no main-loop activity, reboot CLB.

Definition at line 107 of file cfg_soc.h.

#define WRX_BASE   (0x000001FF80)

WhiteRabbit exchange address, not a real device.

WhiteRabbit eXchange.

Definition at line 94 of file cfg_soc.h.