KM3NeT CLB  2.0
KM3NeT CLB v2 Embedded Software
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dev_soc.h
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1 /*
2  * KM3NeT CLB v2 Firmware
3  * ----------------------
4  *
5  * Copyright 2013 KM3NeT Collaboration
6  *
7  * All Rights Reserved.
8  *
9  *
10  * File : devices.h
11  * Created : 22 mrt. 2013
12  * Author : Vincent van Beveren
13  */
14 
15 
16 #ifndef DEV_SOC_H_
17 #define DEV_SOC_H_
18 
19 /**
20  * @file
21  *
22  * @ingroup devices
23  *
24  * This file assigns all device structures to memory mapped structures.
25  *
26  * Memory mapped devices can simply be called using pointer syntax:
27  * @code
28  * TIMER->TICS
29  * @endcode
30  *
31  * \attention most devices also have driver code, simplifying access to the peripheral.
32  * \see drivers
33  */
34 
35 #include "cfg_soc.h"
36 
37 
38 #include "lm32soc/dev_suart.h"
39 #include "lm32soc/dev_acou.h"
40 #include "lm32soc/dev_gpio.h"
41 #include "lm32soc/dev_i2c.h"
42 #include "lm32soc/dev_spi.h"
43 #include "lm32soc/dev_timer.h"
44 #include "lm32soc/dev_daterev.h"
45 #include "lm32soc/dev_ipm.h"
46 #include "lm32soc/dev_mboot.h"
47 #include "lm32soc/dev_tdc.h"
48 #include "lm32soc/dev_stmach.h"
49 #include "lm32soc/dev_nanob.h"
50 #include "lm32soc/dev_xadc.h"
51 #include "lm32soc/dev_watchdog.h"
52 
53 
54 // NOTE: SDB does not really fit into the device-like mapping, so we don't have a dev_* definition.
55 // if you really wish to know what is in there look at sdb.c's structures
56 #define SDB ((void *) SDB_BASE) ///< Self Describing Bus
57 #define SUART1 ((SUART_Device *) SUART1_BASE) ///< SUART base pointer.
58 #define ACOU ((ACOU_Device *) ACOU_BASE) ///< Acou base pointer.
59 #define TDC ((TDC_Device *) TDC_BASE) ///< TDC base pointer.
60 #define MBOOT ((MBOOT_Device *) MBOOT_BASE) ///< Multiboot base pointer.
61 #define STMACH ((STMACH_Device *) STMACH_BASE) ///< State Machine base pointer.
62 #define GPIO ((GPIO_Device *) GPIO_BASE) ///< GPIO base pointer.
63 #define I2C ((I2C_Device *) I2C_BASE) ///< Real OpenCores I2C
64 #define I2C1 ((I2C_Device *) I2C1_BASE) ///< Virtual OpenCores I2C
65 #define I2C2 ((I2C_Device *) I2C2_BASE) ///< Virtual OpenCores I2C
66 #define I2C3 ((I2C_Device *) I2C3_BASE) ///< Virtual OpenCores I2C
67 #define TIMER ((TIMER_Device *) TIMER_BASE) ///< TIMER base pointer.
68 #define DATEREV ((unsigned int *) DATEREV_BASE) ///< Date/Revision Device
69 #define SPI ((SPI_Device *) SPI_BASE) ///< SPI memory mapped structure
70 #define IPMCTRL ((IPMCTRL_Device *) IPMCTRL_BASE) ///< IPMux Control
71 #define IPMPKGEN ((IPMPKGEN_Device *) (IPMCTRL_BASE + 0x40)) ///< IPMux Control
72 #define IPMFIFO ((IPMFIFO_Device *) IPMFIFO_BASE) ///< IPMux FIFO
73 #define NANOB ((NANOB_Device *) NANOB_BASE) ///< Nano-Beacon device
74 #define XADC ((XADC_Device *) XADC_BASE) ///< XADC device
75 #define SUART2 ((SUART_Device *) SUART2_BASE) ///< SUART2 base pointer.
76 #define SUART3 ((SUART_Device *) SUART3_BASE) ///< SUART3 base pointer.
77 #define SUART4 ((SUART_Device *) SUART4_BASE) ///< SUART4 base pointer.
78 
79 #define PTP_SUART ((SUART_Device *) PTP_VUART) ///< PTP UART in WR space
80 
81 #define WATCHDOG ((WATCHDOG_Device *) WATCHDOG_BASE) ///< Watchdog device.
82 
83 #endif /* DEV_SOC_H_ */
This provides a device mapping for a wishbone bus mapped Nano Beacon.
Defines the configuration of the LM32 SOC for the CLBv2.
This provides a device mapping for the OpenCores I2C peripheral.
IPM Device description.
White Rabbit Simple UART register declarations and bitfields.
This provides a device mapping for a wishbone bus mapped Acoustic device.
This provides a device mapping for a wishbone bus mapped GPIO device.
This structure describes the multiboot device.
This provides some defines for reading the date and revision.
Timer Device.
This provides a device mapping for a wishbone bus mapped Watchdog.
XADC register definition.
This provides a device mapping for a wishbone bus mapped State Machine device.
OpenCores SPI device.
This provides a device mapping for a wishbone bus mapped TDCs device.