35 #define SDB_ID_STMACH 0xEFD57BF6
37 #define STMACH_CH_TDC_IDX 0
38 #define STMACH_CH_AES_IDX 1
39 #define STMACH_CH_MCH_IDX 2
41 #define STMACH_CH_TDC BIT(0)
42 #define STMACH_CH_AES BIT(1)
43 #define STMACH_CH_MCH BIT(2)
45 #define STMACH_PL_SIZE_MIN 28
46 #define STMACH_PL_SIZE_MAX 8972
48 #define STMACH_CSR_ENA_MASK 0x00000007
49 #define STMACH_CSR_ENA_SHIFT 0
50 #define STMACH_CSR_SYNC BIT(3)
51 #define STMACH_CSR_FLUSH_MASK 0x00000070
52 #define STMACH_CSR_FLUSH_SHIFT 4
53 #define STMACH_CSR_MCH_BUSY BIT(10)
55 #define STMACH_TDC_FULL_MASK_ALL 0xFFFFFFFF
56 #define STMACH_AES_FULL_MASK_ALL 0x80000001
57 #define STMACH_XXX_FULL_MASK_NONE 0x00000000
60 #define STMACH_ST_COMMIT_AES_SHIFT 0
61 #define STMACH_ST_COMMIT_AES_MASK MASK(16) << STMACH_ST_COMMIT_AES_SHIFT
63 #define STMACH_ST_COMMIT_TDC_SHIFT 16
64 #define STMACH_ST_COMMIT_TDC_MASK MASK(16) << STMACH_ST_COMMIT_TDC_SHIFT
volatile unsigned int PL_SIZE
Maximum payload size (0x00)
volatile unsigned int TDC_FULL_MASK
TDC full MASK (0x20)
volatile unsigned int AES_FULL_MASK
AES full MASK (0x28)
volatile unsigned int MMEM_BASE
Monitor memory base offset for software monitoring data (0x14)
volatile unsigned int TSLICE_LEN
Time slice length (0x0C)
#define reg_i
Read-only register.
volatile unsigned int AES_FULL_IRQ
AES full IRQ (0x24)
volatile unsigned int DOM_ID
DOM identifier (0x04)
const volatile unsigned int ST_COMMIT
AES and TDC super time fifo commit (0x2C)
volatile unsigned int TDC_FULL_IRQ
TDC full IRQ (0x1C)
volatile unsigned int RUN_NUM
Run number (0x08)
volatile unsigned int MMEM_WORDS
Monitor memory length in words. (0x18)
#define reg_io
Input/Output register.
Structure defines State Machine device.
volatile unsigned int CSR
Control Status Register (0x10)
This module contains some very basic type definitions used for hardware mappings. ...