KM3NeT CLB  2.0
KM3NeT CLB v2 Embedded Software
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dev_stmach.h
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1 /*
2  * KM3NeT CLB v2 Firmware
3  * ----------------------
4  *
5  * Copyright 2013 KM3NeT Collaboration
6  *
7  * All Rights Reserved.
8  *
9  *
10  * File : dev_stmach.h
11  * Created : 28 Nov 2013
12  * Author : David Calvo
13  */
14 
15 
16 #ifndef DEV_STMACH_H_
17 #define DEV_STMACH_H_
18 
19 #include "dev_defs.h"
20 
21 
22 /**
23  * @file
24  *
25  * @ingroup devices
26  *
27  * This provides a device mapping for a wishbone bus mapped State Machine device.
28  *
29  * The state machine supports up to four input channels. Currently only 3 are used:
30  * - 0: TDC
31  * - 1: AES
32  * - 2: Monitor channel
33  */
34 
35 #define SDB_ID_STMACH 0xEFD57BF6
36 
37 #define STMACH_CH_TDC_IDX 0 ///< Index of state machine TDC channel
38 #define STMACH_CH_AES_IDX 1 ///< Index of state machine AES channel
39 #define STMACH_CH_MCH_IDX 2 ///< Index of state machine Monitoring channel
40 
41 #define STMACH_CH_TDC BIT(0) ///< Bit of machine TDC channel, relative
42 #define STMACH_CH_AES BIT(1) ///< Bit of state machine AES channel, relative
43 #define STMACH_CH_MCH BIT(2) ///< Bit of state machine Monitoring channel, relative
44 
45 #define STMACH_PL_SIZE_MIN 28
46 #define STMACH_PL_SIZE_MAX 8972
47 
48 #define STMACH_CSR_ENA_MASK 0x00000007 ///< Channel enable mask
49 #define STMACH_CSR_ENA_SHIFT 0 ///< Channel enable shift
50 #define STMACH_CSR_SYNC BIT(3) ///< Indicates the state machine is syncing the enable state.
51 #define STMACH_CSR_FLUSH_MASK 0x00000070 ///< Channel flush mask
52 #define STMACH_CSR_FLUSH_SHIFT 4 ///< Channel flush shift
53 #define STMACH_CSR_MCH_BUSY BIT(10) ///< Monitoring channel busy
54 
55 #define STMACH_TDC_FULL_MASK_ALL 0xFFFFFFFF //!< Mask of all bits indicating TDC full
56 #define STMACH_AES_FULL_MASK_ALL 0x80000001 //!< Mask fo all bits indicating AES full
57 #define STMACH_XXX_FULL_MASK_NONE 0x00000000 //!< Indicates no masking.
58 
59 //! AES commit mask
60 #define STMACH_ST_COMMIT_AES_SHIFT 0
61 #define STMACH_ST_COMMIT_AES_MASK MASK(16) << STMACH_ST_COMMIT_AES_SHIFT
62 //! TDC commit mask
63 #define STMACH_ST_COMMIT_TDC_SHIFT 16
64 #define STMACH_ST_COMMIT_TDC_MASK MASK(16) << STMACH_ST_COMMIT_TDC_SHIFT
65 
66 /**
67  * Structure defines State Machine device.
68  */
69 typedef struct
70 {
71  reg_io PL_SIZE; ///< Maximum payload size (0x00)
72  reg_io DOM_ID; ///< DOM identifier (0x04)
73  reg_io RUN_NUM; ///< Run number (0x08)
74  reg_io TSLICE_LEN; ///< Time slice length (0x0C)
75  reg_io CSR; ///< Control Status Register (0x10)
76  reg_io MMEM_BASE; ///< Monitor memory base offset for software monitoring data (0x14)
77  reg_io MMEM_WORDS; ///< Monitor memory length in words. (0x18)
78  reg_io TDC_FULL_IRQ; ///< TDC full IRQ (0x1C)
79  reg_io TDC_FULL_MASK; ///< TDC full MASK (0x20)
80  reg_io AES_FULL_IRQ; ///< AES full IRQ (0x24)
81  reg_io AES_FULL_MASK; ///< AES full MASK (0x28)
82  reg_i ST_COMMIT; ///< AES and TDC super time fifo commit (0x2C)
84 
85 #endif /* DEV_STMACH_H_ */
86 
volatile unsigned int PL_SIZE
Maximum payload size (0x00)
Definition: dev_stmach.h:71
volatile unsigned int TDC_FULL_MASK
TDC full MASK (0x20)
Definition: dev_stmach.h:79
volatile unsigned int AES_FULL_MASK
AES full MASK (0x28)
Definition: dev_stmach.h:81
volatile unsigned int MMEM_BASE
Monitor memory base offset for software monitoring data (0x14)
Definition: dev_stmach.h:76
volatile unsigned int TSLICE_LEN
Time slice length (0x0C)
Definition: dev_stmach.h:74
#define reg_i
Read-only register.
Definition: dev_defs.h:39
volatile unsigned int AES_FULL_IRQ
AES full IRQ (0x24)
Definition: dev_stmach.h:80
volatile unsigned int DOM_ID
DOM identifier (0x04)
Definition: dev_stmach.h:72
const volatile unsigned int ST_COMMIT
AES and TDC super time fifo commit (0x2C)
Definition: dev_stmach.h:82
volatile unsigned int TDC_FULL_IRQ
TDC full IRQ (0x1C)
Definition: dev_stmach.h:78
volatile unsigned int RUN_NUM
Run number (0x08)
Definition: dev_stmach.h:73
volatile unsigned int MMEM_WORDS
Monitor memory length in words. (0x18)
Definition: dev_stmach.h:77
#define reg_io
Input/Output register.
Definition: dev_defs.h:33
Structure defines State Machine device.
Definition: dev_stmach.h:69
volatile unsigned int CSR
Control Status Register (0x10)
Definition: dev_stmach.h:75
This module contains some very basic type definitions used for hardware mappings. ...