56 #define SDB ((void *) SDB_BASE)
57 #define SUART1 ((SUART_Device *) SUART1_BASE)
58 #define ACOU ((ACOU_Device *) ACOU_BASE)
59 #define TDC ((TDC_Device *) TDC_BASE)
60 #define MBOOT ((MBOOT_Device *) MBOOT_BASE)
61 #define STMACH ((STMACH_Device *) STMACH_BASE)
62 #define GPIO ((GPIO_Device *) GPIO_BASE)
63 #define I2C ((I2C_Device *) I2C_BASE)
64 #define I2C1 ((I2C_Device *) I2C1_BASE)
65 #define I2C2 ((I2C_Device *) I2C2_BASE)
66 #define I2C3 ((I2C_Device *) I2C3_BASE)
67 #define TIMER ((TIMER_Device *) TIMER_BASE)
68 #define DATEREV ((unsigned int *) DATEREV_BASE)
69 #define SPI ((SPI_Device *) SPI_BASE)
70 #define IPMCTRL ((IPMCTRL_Device *) IPMCTRL_BASE)
71 #define IPMPKGEN ((IPMPKGEN_Device *) (IPMCTRL_BASE + 0x40))
72 #define IPMFIFO ((IPMFIFO_Device *) IPMFIFO_BASE)
73 #define NANOB ((NANOB_Device *) NANOB_BASE)
74 #define XADC ((XADC_Device *) XADC_BASE)
75 #define SUART2 ((SUART_Device *) SUART2_BASE)
76 #define SUART3 ((SUART_Device *) SUART3_BASE)
77 #define SUART4 ((SUART_Device *) SUART4_BASE)
79 #define PTP_SUART ((SUART_Device *) PTP_VUART)
81 #define WATCHDOG ((WATCHDOG_Device *) WATCHDOG_BASE)
This provides a device mapping for a wishbone bus mapped Nano Beacon.
Defines the configuration of the LM32 SOC for the CLBv2.
This provides a device mapping for the OpenCores I2C peripheral.
White Rabbit Simple UART register declarations and bitfields.
This provides a device mapping for a wishbone bus mapped Acoustic device.
This provides a device mapping for a wishbone bus mapped GPIO device.
This structure describes the multiboot device.
This provides some defines for reading the date and revision.
This provides a device mapping for a wishbone bus mapped Watchdog.
XADC register definition.
This provides a device mapping for a wishbone bus mapped State Machine device.
This provides a device mapping for a wishbone bus mapped TDCs device.