30 #define SDB_ID_I2C 0x6B9456E4
32 #define I2C_CMD_IACK BIT(0)
33 #define I2C_CMD_ACK BIT(3)
34 #define I2C_CMD_WR BIT(4)
35 #define I2C_CMD_RD BIT(5)
36 #define I2C_CMD_STOP BIT(6)
37 #define I2C_CMD_START BIT(7)
39 #define I2C_STS_IRQ BIT(0)
40 #define I2C_STS_TIP BIT(1)
41 #define I2C_STS_ARBLOST BIT(5)
42 #define I2C_STS_BUSY BIT(6)
43 #define I2C_STS_RXACK BIT(7)
45 #define I2C_CTL_INT_ENA BIT(6)
46 #define I2C_CTL_CORE_ENA BIT(7)
48 #define I2C_IF_NO_MASK 0x0F
49 #define I2C_IF_NO_SHIFT 0
50 #define I2C_IF_BUSY BIT(7)
volatile unsigned int PRE_HI
Prescaler high.
volatile unsigned int PRE_LO
Prescaler low.
volatile unsigned int CTL
Control.
volatile unsigned int IF
Interface no. register (WR extension)
Structure defines OpenCores I2C Device.
volatile unsigned int TXRX
Transmit / Receive.
volatile unsigned int CMDSTS
Command and Status.
#define reg_io
Input/Output register.
This module contains some very basic type definitions used for hardware mappings. ...